Assembler and ABI Resources: what changed

Revision 0 to 1. Removed lines have a minus sign; added lines have a plus sign.

Title: Assembler and ABI Resources

New		Line
1	+	## The Assembler
2	+
3	+	The FPC Pascal Compiler translates Pascal source code into assembly language which is then processed by an assembler running as a separate backend. Some other Pascal compilers directly generate object modules or executable programs directly, i.e. they do not require a separate assembler.
4	+
5	+	An assembler is itself an executable program that translates assembly language into an object module. In most cases the object modules are passed to a linker which then produces an executable program, although in some there are additional stages (code signing for secure operating systems, conversion to a binary for embedded systems and so on).
6	+
7	+	## The ABI
8	+
9	+	The interface between an executable program and the underlying operating system is referred to as the Application Binary Interface or ABI. This includes the CPU's operating mode (e.g. whether word and address sizes default to 32 or 64 bits), operand alignment, function calling conventions, system call numbers, and a selection of constants (e.g. file open modes) and structures (e.g. as returned by the stat() function). It is also usually considered to include the format of the object modules, executable and library files.
10	+
11	+	Obviously the ABI is grossly different between operating systems: in general a program compiled for Windows will not run on Linux and vice versa. In addition, however, there is a significant amount of variation between different "flavours" of related operating systems, for example not only are the system call numbers different between SPARC Solaris and SPARC Linux but they are different between SPARC Linux and x86 Linux.
12	+
13	+	## Purpose of this note
14	+
15	+	In most cases FPC uses the GNU assembler ("as" or "gas") as its backend. However, the assembly language syntax expected by this is different for each target CPU, sections below give examples of this. The original incentive for this was because the author (MarkMLl) found that he needed to write an assembler reader for the MIPS processor, and that there was no straightforward comparison of existing formats on which he could base new code.
16	+
17	+	In addition, in some cases the details of the assembly language format or the ABI specification are only available to users registered with the relevant manufacturer, where possible links to unofficial mirrors are given below for casual reference.
18	+
19	+	## Assembler source formats
20	+
21	+	Assembler source emitted by the compiler's code generator has to be (a subset of what is) acceptable to the assembler for the relevant target CPU. In addition, small portions of the RTL (e.g. prt0.as) are of necessity written in assembler, and some Pascal source files (e.g. syscall.inc) contain inline assembler which the compiler has to be able to parse before it is passed to the backend.
22	+
23	+	The list of CPUs below is taken from the compiler as of late 2011. Some of these are no longer supported, or exist merely as minimal stubs.
24	+
25	+	### Alpha
26	+
27	+	This compiler exists only as a minimal stub.
28	+
29	+	### ARM
30	+
31	+	This fragment is from FpSysCall alias FPC_SYSCALL6 in FPC's ./rtl/linux/arm/syscall.inc:
32	+
33	+	`asm`\
34	+	` stmfd sp!,{r4,r5,r6}`\
35	+	` ldr r4,param4`\
36	+	` ldr r5,param5`\
37	+	` ldr r6,param6`\
38	+	` bl FPC_SYSCALL`\
39	+	` ldmfd sp!,{r4,r5,r6}`\
40	+	`end;`
41	+
42	+	This fragment is from ret_from_fork in Linux's ./arch/arm/kernel/entry-common.S:
43	+
44	+	`ENTRY(ret_from_fork)`\
45	+	` bl schedule_tail`\
46	+	` get_thread_info tsk`\
47	+	` ldr r1, [tsk, #TI_FLAGS] @ check for syscall tracing`\
48	+	` mov why, #1`\
49	+	` tst r1, #_TIF_SYSCALL_TRACE @ are we tracing syscalls?`\
50	+	` beq ret_slow_syscall`\
51	+	` mov r1, sp`\
52	+	` mov r0, #1 @ trace exit [IP = 1]`\
53	+	` bl syscall_trace`\
54	+	` b ret_slow_syscall`\
55	+	`ENDPROC(ret_from_fork)`
56	+
57	+	Note that register names are r0, r1 etc. without a sigil, and that register assignment is right-to-left.
58	+
59	+	### AVR
60	+
61	+	This fragment is from part of fpc's startup code in /rtl/embedded/avr/start.inc:
62	+
63	+	` _start:`\
64	+	` {$ifdef CPUAVR_16_REGS}`\
65	+	` clr r17`\
66	+	` {$else CPUAVR_16_REGS}`\
67	+	` clr r1`\
68	+	` {$endif CPUAVR_16_REGS}`\
69	+	\
70	+	` // load stack pointer`\
71	+	` ldi r30,lo8(_stack_top)`\
72	+	` out 0x3d,r30`\
73	+	` ldi r30,hi8(_stack_top)`\
74	+	` out 0x3e,r30`\
75	+	\
76	+	` // Initialize .data section`\
77	+	` ldi XL,lo8(_data)`\
78	+	` ldi XH,hi8(_data)`\
79	+	` ldi YH,hi8(_edata)`\
80	+	` ldi ZL,lo8(_etext)`\
81	+	` {$ifdef CPUAVR_16_REGS}`\
82	+	` ldi ZH,hi8(_etext)+(0x40) // program memory mapped to $4000 in data space`\
83	+	` {$else CPUAVR_16_REGS}`\
84	+	` ldi ZH,hi8(_etext)`\
85	+	` {$endif CPUAVR_16_REGS}`
86	+
87	+	Note that register names are r0, r1 etc. without a sigil, and that register assignment is right-to-left.
88	+
89	+	### i386
90	+
91	+	This fragment is from FpSysCall alias FPC_SYSCALL6 in FPC's ./rtl/linux/i386/syscall.inc:
92	+
93	+	`asm`\
94	+	` push %ebx`\
95	+	` push %edx`\
96	+	` push %esi`\
97	+	` push %edi`\
98	+	` push %ebp`\
99	+	` push %ecx`\
100	+	` cmp $0, sysenter_supported`\
101	+	` jne .LSysEnter`\
102	+	` movl %edx,%ebx // param1`\
103	+	` pop %ecx // param2`\
104	+	` movl param3,%edx // param3`\
105	+	` movl param4,%esi // param4`\
106	+	` movl param5,%edi // param5`\
107	+	` movl param6,%ebp // param6`\
108	+	` int $0x80`\
109	+	` jmp .LTail`\
110	+	` .LSysEnter:`\
111	+	` movl %edx,%ebx // param1`\
112	+	` pop %ecx // param2`\
113	+	` movl param3,%edx // param3`\
114	+	` movl param4,%esi // param4`\
115	+	` movl param5,%edi // param5`\
116	+	` movl param6,%ebp // param6`\
117	+	` call psysinfo`\
118	+	` .LTail:`\
119	+	` pop %ebp`\
120	+	` pop %edi`\
121	+	` pop %esi`\
122	+	` pop %edx`\
123	+	` pop %ebx`\
124	+	` cmpl $-4095,%eax`\
125	+	` jb .LSyscOK`\
126	+	` negl %eax`\
127	+	` call seterrno`\
128	+	` movl $-1,%eax`\
129	+	` .LSyscOK:`\
130	+	`end;`
131	+
132	+	This fragment is from ret_from_fork in Linux's ./arch/x86/kernel/entry_32.S:
133	+
134	+	`ENTRY(ret_from_fork)`\
135	+	` CFI_STARTPROC`\
136	+	` pushl %eax`\
137	+	` CFI_ADJUST_CFA_OFFSET 4`\
138	+	` call schedule_tail`\
139	+	` GET_THREAD_INFO(%ebp)`\
140	+	` popl %eax`\
141	+	` CFI_ADJUST_CFA_OFFSET -4`\
142	+	` pushl $0x0202 # Reset kernel eflags`\
143	+	` CFI_ADJUST_CFA_OFFSET 4`\
144	+	` popfl`\
145	+	` CFI_ADJUST_CFA_OFFSET -4`\
146	+	` jmp syscall_exit`\
147	+	` CFI_ENDPROC`\
148	+	`END(ret_from_fork)`
149	+
150	+	Note that register names are eax, ebx etc. with % as a mandatory sigil, and that register assignment is left-to-right.
151	+
152	+	### IA-64
153	+
154	+	This compiler exists only as a minimal stub.
155	+
156	+	### M68K
157	+
158	+	This compiler exists in FPC v1 and has lain dormant for a while but has since inclusion in FPC 2.x in the end of 2013.
159	+
160	+	### MIPS
161	+
162	+	This fragment is from FpSysCall alias FPC_SYSCALL6 in FPC's ./rtl/linux/mips/syscall.inc:
163	+
164	+	`asm`\
165	+	` sw $4,0($23)`\
166	+	` sw $5,-4($23)`\
167	+	` sw $6,-8($23)`\
168	+	` sw $7,-12($23)`\
169	+	` sw $8,-16($23)`\
170	+	` sw $9,-20($23)`\
171	+	` sw $10,-24($23)`\
172	+	` sw $11,-28($23)`\
173	+	` sw $12,-32($23)`\
174	+	` sw $13,-36($23)`\
175	+	` sw $14,-40($23)`\
176	+	` addiu $23,$23,-44`\
177	+	\
178	+	` move $2,$4`\
179	+	` move $4,$5`\
180	+	` move $5,$6`\
181	+	` move $6,$7`\
182	+	` move $7,$8`\
183	+	` move $8,$9`\
184	+	` lw $9,0($fp)`\
185	+	\
186	+	` subu $29,32`\
187	+	` sw $8, 16($29)`\
188	+	` sw $9, 20($29)`\
189	+	` syscall`\
190	+	` nop`\
191	+	` addiu $29,32`\
192	+	\
193	+	` beq $7,$0,.LDone`\
194	+	` nop`\
195	+	` lui $8,%hi(fpc_threadvar_relocate_proc)`\
196	+	` addiu $8,%lo(fpc_threadvar_relocate_proc)`\
197	+	` lw $8,0($8)`\
198	+	` bne $8,$0,.LThreaded`\
199	+	` nop`\
200	+	` lui $4,%hi(Errno+4)`\
201	+	` addiu $4,%lo(Errno+4)`\
202	+	` sw $2,0($4)`\
203	+	` b .LFailed`\
204	+	` nop`\
205	+	`.LThreaded:`\
206	+	` sw $2,-4($fp)#temp#sw $4`\
207	+	` lui $4,%hi(errno)`\
208	+	` addiu $4,$4,%lo(errno)`\
209	+	` jal $8`\
210	+	` nop`\
211	+	` lw $8,-4($fp)`\
212	+	` sw $8,0($2)`\
213	+	`.LFailed:`\
214	+	` li $2,-1`\
215	+	`.LDone:`\
216	+	\
217	+	` addiu $23,$23,44`\
218	+	` lw $4,0($23)`\
219	+	` lw $5,-4($23)`\
220	+	` lw $6,-8($23)`\
221	+	` lw $7,-12($23)`\
222	+	` lw $8,-16($23)`\
223	+	` lw $9,-20($23)`\
224	+	` lw $10,-24($23)`\
225	+	` lw $11,-28($23)`\
226	+	` lw $12,-32($23)`\
227	+	` lw $13,-36($23)`\
228	+	` lw $14,-40($23)`\
229	+	\
230	+	`end;`
231	+
232	+	This fragment is from ret_from_fork in Linux's ./arch/mips/kernel/entry.S:
233	+
234	+	`FEXPORT(ret_from_fork)`\
235	+	` jal schedule_tail # a0 = struct task_struct *prev`\
236	+	\
237	+	`FEXPORT(syscall_exit)`\
238	+	` local_irq_disable # make sure need_resched and`\
239	+	` # signals dont change between`\
240	+	` # sampling and return`\
241	+	` LONG_L a2, TI_FLAGS($28) # current->work`\
242	+	` li t0, _TIF_ALLWORK_MASK`\
243	+	` and t0, a2, t0`\
244	+	` bnez t0, syscall_exit_work`\
245	+	\
246	+	`FEXPORT(restore_all) # restore full frame`\
247	+	` .set noat`\
248	+	` RESTORE_TEMP`\
249	+	` RESTORE_AT`\
250	+	` RESTORE_STATIC`\
251	+	`FEXPORT(restore_partial) # restore partial frame`\
252	+	` RESTORE_SOME`\
253	+	` RESTORE_SP_AND_RET`\
254	+	` .set at`
255	+
256	+	Note that register names are 0, 1 etc. with \$ as a mandatory sigil, and that register assignment is right-to-left; versions of GNU as from 2.18 onwards also support symbolic register names a0, a1 etc. There is a delay slot after branch etc. instructions.
257	+
258	+	### PowerPC
259	+
260	+	This fragment is from FpSysCall alias FPC_SYSCALL6 in FPC's ./rtl/linux/powerpc/syscall.inc:
261	+
262	+	`asm`\
263	+	` mr r0,r3`\
264	+	` mr r3,r4`\
265	+	` mr r4,r5`\
266	+	` mr r5,r6`\
267	+	` mr r6,r7`\
268	+	` mr r7,r8`\
269	+	` mr r8,r9`\
270	+	` sc`\
271	+	` bns .LDone`\
272	+	` lis r10,(fpc_threadvar_relocate_proc)@ha`\
273	+	` lwz r10,(fpc_threadvar_relocate_proc)@l(r10)`\
274	+	` cmpwi r10,0`\
275	+	` bne .LThreaded`\
276	+	` lis r4,(Errno+4)@ha`\
277	+	` stw r3,(Errno+4)@l(r4)`\
278	+	` b .LFailed`\
279	+	`.LThreaded:`\
280	+	` stw r3,temp`\
281	+	` mflr r3`\
282	+	` mtctr r10`\
283	+	` lis r4,(errno)@ha`\
284	+	` stw r3,retaddress`\
285	+	` lwz r3,(errno)@l(r4)`\
286	+	` bctrl`\
287	+	` lwz r4,temp`\
288	+	` lwz r5,retaddress`\
289	+	` stw r4,0(r3)`\
290	+	` mtlr r5`\
291	+	`.LFailed:`\
292	+	` li r3,-1`\
293	+	`.LDone:`\
294	+	`end;`
295	+
296	+	This fragment is from ret_from_fork in Linux's ./arch/powerpc/kernel/entry_32.S:
297	+
298	+	`ret_from_syscall:`\
299	+	` mr r6,r3`\
300	+	` rlwinm r12,r1,0,0,(31-THREAD_SHIFT) /* current_thread_info() */`\
301	+	` /* disable interrupts so current_thread_info()->flags can't change */`\
302	+	` LOAD_MSR_KERNEL(r10,MSR_KERNEL) /* doesn't include MSR_EE */`\
303	+	` /* Note: We don't bother telling lockdep about it */`\
304	+	` SYNC`\
305	+	` MTMSRD(r10)`\
306	+	` lwz r9,TI_FLAGS(r12)`\
307	+	` li r8,-_LAST_ERRNO`\
308	+	` andi. r0,r9,(_TIF_SYSCALL_T_OR_A\|_TIF_SINGLESTEP\|_TIF_USER_WORK_MASK\|_TIF_PERSYSCALL_MASK)`\
309	+	` bne- syscall_exit_work`\
310	+	` cmplw 0,r3,r8`\
311	+	` blt+ syscall_exit_cont`\
312	+	` lwz r11,_CCR(r1) /* Load CR */`\
313	+	` neg r3,r3`\
314	+	` oris r11,r11,0x1000 /* Set SO bit in CR */`\
315	+	` stw r11,_CCR(r1)`\
316	+	`syscall_exit_cont:`\
317	+	` lwz r8,_MSR(r1)`\
318	+	`BEGIN_FTR_SECTION`\
319	+	` lwarx r7,0,r1`\
320	+	`END_FTR_SECTION_IFSET(CPU_FTR_NEED_PAIRED_STWCX)`\
321	+	` stwcx. r0,0,r1 /* to clear the reservation */`\
322	+	` lwz r4,_LINK(r1)`\
323	+	` lwz r5,_CCR(r1)`\
324	+	` mtlr r4`\
325	+	` mtcr r5`\
326	+	` lwz r7,_NIP(r1)`\
327	+	` FIX_SRR1(r8, r0)`\
328	+	` lwz r2,GPR2(r1)`\
329	+	` lwz r1,GPR1(r1)`\
330	+	` mtspr SPRN_SRR0,r7`\
331	+	` mtspr SPRN_SRR1,r8`\
332	+	` SYNC`\
333	+	` RFI`\
334	+	\
335	+	`66: li r3,-ENOSYS`\
336	+	` b ret_from_syscall`\
337	+	\
338	+	`ret_from_fork:`\
339	+	` REST_NVGPRS(r1)`\
340	+	` bl schedule_tail`\
341	+	` li r3,0`\
342	+	` b ret_from_syscall`
343	+
344	+	Note that register names are r0, r1 etc. without a sigil, and that register assignment is right-to-left.
345	+
346	+	### PowerPC-64
347	+
348	+	Similar to PowerPC above.
349	+
350	+	### SPARC
351	+
352	+	This fragment is from FpSysCall alias FPC_SYSCALL6 in FPC's ./rtl/linux/sparc/syscall.inc:
353	+
354	+	`asm`\
355	+	` mov %i0,%g1`\
356	+	` mov %i1,%o0`\
357	+	` mov %i2,%o1`\
358	+	` mov %i3,%o2`\
359	+	` mov %i4,%o3`\
360	+	` ld [%i6+92],%o5`\
361	+	` mov %i5,%o4`\
362	+	` ta 0x10`\
363	+	` bcc .LSyscOK`\
364	+	` nop`\
365	+	` mov %o0,%l0`\
366	+	` sethi %hi(fpc_threadvar_relocate_proc),%o2`\
367	+	` or %o2,%lo(fpc_threadvar_relocate_proc),%o2`\
368	+	` ld [%o2],%o3`\
369	+	` subcc %o3,%g0,%g0`\
370	+	` bne .LThread`\
371	+	` nop`\
372	+	` sethi %hi(Errno+4),%o0`\
373	+	` ba .LNoThread`\
374	+	` or %o0,%lo(Errno+4),%o0`\
375	+	`.LThread:`\
376	+	` sethi %hi(Errno),%o0`\
377	+	` or %o0,%lo(Errno),%o0`\
378	+	` call %o3`\
379	+	` ld [%o0],%o0`\
380	+	`.LNoThread:`\
381	+	` st %l0,[%o0]`\
382	+	` mov -1,%o0`\
383	+	`.LSyscOK:`\
384	+	` mov %o0,%i0`\
385	+	`end;`
386	+
387	+	This fragment is from ret_from_fork in Linux's ./arch/sparc/kernel/entry.S:
388	+
389	+	`linux_fast_syscall:`\
390	+	` andn %l7, 3, %l7`\
391	+	` mov %i0, %o0`\
392	+	` mov %i1, %o1`\
393	+	` mov %i2, %o2`\
394	+	` jmpl %l7 + %g0, %g0`\
395	+	` mov %i3, %o3`\
396	+	\
397	+	`linux_syscall_trace:`\
398	+	` add %sp, STACKFRAME_SZ, %o0`\
399	+	` call syscall_trace`\
400	+	` mov 0, %o1`\
401	+	` cmp %o0, 0`\
402	+	` bne 3f`\
403	+	` mov -ENOSYS, %o0`\
404	+	` mov %i0, %o0`\
405	+	` mov %i1, %o1`\
406	+	` mov %i2, %o2`\
407	+	` mov %i3, %o3`\
408	+	` b 2f`\
409	+	` mov %i4, %o4`\
410	+	\
411	+	` .globl ret_from_fork`\
412	+	`ret_from_fork:`\
413	+	` call schedule_tail`\
414	+	` mov %g3, %o0`\
415	+	` b ret_sys_call`\
416	+	` ld [%sp + STACKFRAME_SZ + PT_I0], %o0`\
417	+	\
418	+	` /* Linux native system calls enter here... */`\
419	+	` .align 4`\
420	+	` .globl linux_sparc_syscall`\
421	+	`linux_sparc_syscall:`\
422	+	` sethi %hi(PSR_SYSCALL), %l4`\
423	+	` or %l0, %l4, %l0`\
424	+	` /* Direct access to user regs, must faster. */`\
425	+	` cmp %g1, NR_SYSCALLS`\
426	+	` bgeu linux_sparc_ni_syscall`\
427	+	` sll %g1, 2, %l4`\
428	+	` ld [%l7 + %l4], %l7`\
429	+	` andcc %l7, 1, %g0`\
430	+	` bne linux_fast_syscall`\
431	+	` /* Just do first insn from SAVE_ALL in the delay slot */`
432	+
433	+	Note that register names are i0, i1 etc. with % as a mandatory sigil, and that register assignment is left-to-right. Registers are windowed, and there is a delay slot after branch etc. instructions.
434	+
435	+	### VIS
436	+
437	+	This compiler exists only as a minimal stub.
438	+
439	+	### x86
440	+
441	+	Refer to i386 above.
442	+
443	+	### x86-64
444	+
445	+	This fragment is from FpSysCall alias FPC_SYSCALL6 in FPC's ./rtl/linux/x86_64/syscall.inc:
446	+
447	+	`asm`\
448	+	` movq sysnr, %rax { Syscall number -> rax. }`\
449	+	` movq param1, %rdi { shift arg1 - arg5. }`\
450	+	` movq param2, %rsi`\
451	+	` movq param3, %rdx`\
452	+	` movq param4, %r10`\
453	+	` movq param5, %r8`\
454	+	` movq param6, %r9`\
455	+	` syscall { Do the system call. }`\
456	+	` cmpq $-4095, %rax { Check %rax for error. }`\
457	+	` jnae .LSyscOK { Jump to error handler if error. }`\
458	+	` negq %rax`\
459	+	` movq %rax,%rdx`\
460	+	` movq fpc_threadvar_relocate_proc,%rax`\
461	+	` leaq Errno,%r11`\
462	+	` testq %rax,%rax`\
463	+	` jne .LThread`\
464	+	` movl %edx,8(%r11)`\
465	+	` jmp .LNoThread`\
466	+	`.LThread:`\
467	+	` pushq %rdx`\
468	+	` movq (%r11),%rdi`\
469	+	` call *%rax`\
470	+	` popq %rdx`\
471	+	` movl %edx,(%rax)`\
472	+	`.LNoThread:`\
473	+	` movq $-1,%rax`\
474	+	`.LSyscOK:`\
475	+	`end;`
476	+
477	+	This fragment is from ret_from_fork in Linux's ./arch/x86/kernel/entry_64.S:
478	+
479	+	`ENTRY(ret_from_fork)`\
480	+	` DEFAULT_FRAME`\
481	+	\
482	+	` LOCK ; btr $TIF_FORK,TI_flags(%r8)`\
483	+	\
484	+	` push kernel_eflags(%rip)`\
485	+	` CFI_ADJUST_CFA_OFFSET 8`\
486	+	` popf # reset kernel eflags`\
487	+	` CFI_ADJUST_CFA_OFFSET -8`\
488	+	\
489	+	` call schedule_tail # rdi: 'prev' task parameter`\
490	+	\
491	+	` GET_THREAD_INFO(%rcx)`\
492	+	\
493	+	` RESTORE_REST`\
494	+	\
495	+	` testl $3, CS-ARGOFFSET(%rsp) # from kernel_thread?`\
496	+	` je int_ret_from_sys_call`\
497	+	\
498	+	` testl $_TIF_IA32, TI_flags(%rcx) # 32-bit compat task needs IRET`\
499	+	` jnz int_ret_from_sys_call`\
500	+	\
501	+	` RESTORE_TOP_OF_STACK %rdi, -ARGOFFSET`\
502	+	` jmp ret_from_sys_call # go to the SYSRET fastpath`\
503	+	\
504	+	` CFI_ENDPROC`\
505	+	`END(ret_from_fork)`
506	+
507	+	Note that register names are rax, rbx etc. with % as a mandatory sigil, and that register assignment is left-to-right.
508	+
509	+	### zSeries (S/390)
510	+
511	+	As of early 2012, IBM's [[ZSeries\|zSeries]] (formerly System/390) is not supported by the compiler, refer to [[ZSeries/Part 1]] for the current implementation status. Note that Linux 2.6 probably won't run on anything older than an S/390 G5.
512	+
513	+	#### For the GNU assembler (gas):
514	+
515	+	This fragment is from ret_from_fork in Linux's ./arch/s390/kernel/entry.S:
516	+
517	+	`#define BASED(name) name-system_call(%r13)`\
518	+	\
519	+	` .globl ret_from_fork`\
520	+	`ret_from_fork:`\
521	+	` l %r13,__LC_SVC_NEW_PSW+4`\
522	+	` l %r9,__LC_THREAD_INFO # load pointer to thread_info struct`\
523	+	` tm SP_PSW+1(%r15),0x01 # forking a kernel thread ?`\
524	+	` bo BASED(0f)`\
525	+	` st %r15,SP_R15(%r15) # store stack pointer for new kthread`\
526	+	`0: l %r1,BASED(.Lschedtail)`\
527	+	` basr %r14,%r1`\
528	+	` TRACE_IRQS_ON`\
529	+	` stosm __SF_EMPTY(%r15),0x03 # reenable interrupts`\
530	+	` b BASED(sysc_tracenogo)`\
531	+	\
532	+	`sysc_tracenogo:`\
533	+	` tm __TI_flags+2(%r9),_TIF_SYSCALL`\
534	+	` bz BASED(sysc_return)`\
535	+	` l %r1,BASED(.Ltrace_exit)`\
536	+	` la %r2,SP_PTREGS(%r15) # load pt_regs`\
537	+	` la %r14,BASED(sysc_return)`\
538	+	` br %r1`
539	+
540	+	Note that register names are r0, r1 etc. with % as a mandatory sigil. Older assemblers (below) arranged the operands as ordered in the binary opcode (i.e. register assignment order varies by operation), this might have changed for the GNU assembler resulting in obvious compatibility problems.
541	+
542	+	#### For the IBM assembler:
543	+
544	+	For the purpose of comparison and with minimal comment, here are "Hello, World!" programs compiled with GCC for different targets.
545	+
546	+	`GCCMVS on MUSIC/SP hosted by Sim/390 using the command`\
547	+	\
548	+	`gccmvs_v30 -S -o hello.asm ... hello.c`\
549	+	\
550	+	`generates this:`\
551	+	\
552	+	`LC0 EQU *`\
553	+	` DC C'Hello, MUSIC/SP!'`\
554	+	` DC X'15'`\
555	+	` DC X'0'`\
556	+	` DS 0F`\
557	+	` EXTRN @@CRT0`\
558	+	`* Function main prologue`\
559	+	`MAIN PDPPRLG CINDEX=0,FRAME=92,BASER=12,ENTRY=YES`\
560	+	` B FEN0`\
561	+	` LTORG`\
562	+	`FEN0 EQU *`\
563	+	` DROP 12`\
564	+	` BALR 12,0`\
565	+	` USING *,12`\
566	+	`PG0 EQU *`\
567	+	` LR 11,1`\
568	+	` L 10,=A(PGT0)`\
569	+	`* Function main code`\
570	+	` MVC 88(4,13),=A(LC0)`\
571	+	` LA 1,88(,13)`\
572	+	` L 15,=V(PRINTF)`\
573	+	` BALR 14,15`\
574	+	` SLR 2,2`\
575	+	` LR 15,2`
576	+
577	+	In the example above, note that registers are identified numerically (e.g. BALR 12,0); it is common to load a macro package which introduces a leading R as a sigil (i.e. BALR R12,R0). The operands are ordered as in the binary opcode (i.e. register assignment order varies by operation), this might have changed for the GNU assembler (see section above) resulting in obvious compatibility problems.
578	+
579	+	`GCC on zSeries Linux hosted by Hercules using the command`\
580	+	\
581	+	`gcc -S -o hello.asm hello.c`\
582	+	\
583	+	`apparently assuming -march=g5, generates this:`\
584	+	\
585	+	`.LC0:`\
586	+	` .string "Hello, Linux!"`\
587	+	`.text`\
588	+	` .align 4`\
589	+	`.globl main`\
590	+	` .type main, @function`\
591	+	`main:`\
592	+	`.LFB2:`\
593	+	` stm %r11,%r15,44(%r15)`\
594	+	`.LCFI0:`\
595	+	` basr %r13,0`\
596	+	`.L3:`\
597	+	` ahi %r15,-96`\
598	+	`.LCFI1:`\
599	+	` lr %r11,%r15`\
600	+	`.LCFI2:`\
601	+	` l %r1,.L4-.L3(%r13)`\
602	+	` lr %r2,%r1`\
603	+	` l %r1,.L5-.L3(%r13)`\
604	+	` basr %r14,%r1`\
605	+	` lhi %r1,0`\
606	+	` lr %r2,%r1`\
607	+	` l %r4,152(%r11)`\
608	+	` lm %r11,%r15,140(%r11)`\
609	+	` br %r4`\
610	+	` .align 4`\
611	+	`.L5:`\
612	+	` .long puts`\
613	+	`.L4:`\
614	+	` .long .LC0`\
615	+	\
616	+	`I think that's still effectively generating code similar to traditional`\
617	+	`assembler's "using".`
618	+
619	+	`With the explicit instruction to use a later CPU:`\
620	+	\
621	+	`gcc -march=z900 -S -o hello.asm hello.c`\
622	+	\
623	+	`it generates this:`\
624	+	\
625	+	`.LC0:`\
626	+	` .string "Hello, Linux!"`\
627	+	`.text`\
628	+	` .align 4`\
629	+	`.globl main`\
630	+	` .type main, @function`\
631	+	`main:`\
632	+	`.LFB2:`\
633	+	` stm %r11,%r15,44(%r15)`\
634	+	`.LCFI0:`\
635	+	` ahi %r15,-96`\
636	+	`.LCFI1:`\
637	+	` lr %r11,%r15`\
638	+	`.LCFI2:`\
639	+	` larl %r2,.LC0`\
640	+	` brasl %r14,puts`\
641	+	` lhi %r1,0`\
642	+	` lr %r2,%r1`\
643	+	` l %r4,152(%r11)`\
644	+	` lm %r11,%r15,140(%r11)`\
645	+	` br %r4`\
646	+	\
647	+	`If I'm reading that correctly, it's referring to the string directly`\
648	+	`without using a register.`
649	+
650	+	## ABI references
651	+
652	+	The list of CPUs etc. is based on those found in the compiler (see above).
653	+
654	+	### Alpha
655	+
656	+	### ARM
657	+
658	+	### AVR
659	+
660	+	Currently only the embedded target is supported by FPC. The compiler follows the register layout [1](https://gcc.gnu.org/wiki/avr-gcc#Register_Layout), frame layout [2](https://gcc.gnu.org/wiki/avr-gcc#Frame_Layout) and calling convention [3](https://gcc.gnu.org/wiki/avr-gcc#Calling_Convention) of the avr-gcc ABI.
661	+
662	+	### i386
663	+
664	+	### IA-64
665	+
666	+	### M68K
667	+
668	+	### MIPS
669	+
670	+	MIPS has several kinds of ABI, including O32, EABI, n32, n64, nowadays the de facto one should be O32. Some ABI document for MIPS O32 ABI can be found in the internet, unfortunately due to the copyright limit, we cannot provide it here. However, this page [4](http://www.linux-mips.org/wiki/MIPSABIHistory) has some useful links.
671	+
672	+	### PowerPC
673	+
674	+	### PowerPC-64
675	+
676	+	### SPARC
677	+
678	+	SPARC is an open architecture. All design documents are freely available (no signup required) from sparc.org and opensparc.net. sparc.org has documents on the 32 bit SPARC version V8 and the 64 bit SPARC version V9. Earlier versions of the architecture, specifically V7 are available on the net (search for Solbourne).
679	+
680	+	You can download the SPARC V8 Architecture Manual here: [5](http://sparc.org/standards/V8.pdf) The SPARC V8 ABI for UNIX is here: [6](http://sparc.org/standards/psABI3rd.pdf)
681	+
682	+	You can download the SPARC V9 Architecture Manual here: [7](http://sparc.org/standards/SPARCV9.pdf) The SPARC V9 ABI for UNIX is here: [8](http://sparc.org/standards/SCD.2.4.1.ps.Z) Newer versions than V9 are available on opensparc.net.
683	+
684	+	### VIS
685	+
686	+	### x86
687	+
688	+	### x86-64
689	+
690	+	### zSeries (S/390)
691	+
692	+	The classic IBM operating systems, particularly when running on older hardware (i.e. preceding the S/390 G5) historically adopt a programming style which passes function parameters in registers and blocks of memory rather than using a stack.
693	+
694	+	For Linux on a 32-bit S/390, "The first 5 integer (char, short, int, long, long long) and pointer parameters are passed in registers R2, R3, R4, R5 and R6. ... long long parameters are passed in register pairs. Structures of 1, 2, 4 or 8 bytes are passed as integers. ... the first 2 floating point parameters are passed in F0 and F2. ... All other parameters are passed on the stack. If the return value is not an integer, pointer, float, double or 1, 2, 4 or 9-byte structure, a "hidden" parameter in R2 will contain the address of the return area." [9](http://linuxvm.org/present/SHARE99/S8139db.pdf)
695	+
696	+	## Other resources
697	+
698	+	As a general point, there's some useful thoughts on binary disassembly at <http://chdk.wikia.com/wiki/GPL_Disassembling> for situations where IDA or equivalent aren't available.
699	+
700	+	---
701	+	From the Free Pascal wiki, page "Assembler and ABI Resources", as it stood on 2022-06-18 after a change by Alextp, out of the wiki's dump of 2024-05-26. Copyright stays with the author who wrote it, according to the old wiki's [[Licensing]] page. If you have concerns about this material, [message the admin](/wiki-contact).
702	+	Category: FPC internals

Back to history