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Mailing lists / fpc-devel / 2005-08

Building for powerpc on FC4 seems to fail

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Joost van der Sluis

Hi all,

i'm trying to build fpc 2.0.0 on the Fedora buildsystem, but the build fails for powerpc. The startcompiler gives a segfault.

Micha tried to compile the rpm on his powerpc, and he succeeded, but that's debian.

The question is: is it possible that the switch to gcc-4 on Fedora could cause this problem? Or maybe that a syscall is deprecated in FC-4?

Does anyone has a powerpc available, on which he/she can install Fedora Core 4 to try this?

Or: any other thoughts?

Log of the failed build can be found here. But it doesn't contain the fpc-output: http://buildsys.fedoraproject.org/logs//development/7-fpc-2.0.0-1/ppc/build.log

Regards,
Joost van der Sluis

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Jonas Maebe
to Joost van der Sluis
Joost van der Sluis wrote
i'm trying to build fpc 2.0.0 on the Fedora buildsystem, but the build fails for powerpc. The startcompiler gives a segfault.

The reason is probably that the machine you are building on is a G5. For some reason, the Linux kernel people do not turn on a compatibility bit in the G5 which guarantees the same behaviour for the dcbz instruction as on other PPC's (it's meaning is "fill a cache line with zeroes", but cache lines on G5's are 128 bytes as opposed to 32 bytes on other ppc's and many programs, including the FPC rtl, count on that -- which is the reason why this compatibility bit exists and why the G5 also has a dcbzl instruction which zeroes out a full 128 bytes in all cases).

Anyway, the result is that too much memory is zeroed out by some RTL routines. You can solve it by disabling all routines rtl/powerpc/ *.inc which include the dcbz instruction and then rebuilding the compiler on a non-G5 machine.

Jonas

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Joost van der Sluis
to Jonas Maebe
Jonas Maebe wrote 19 lines
On 16 aug 2005, at 15:43, Joost van der Sluis wrote: > i'm trying to build fpc 2.0.0 on the Fedora buildsystem, but the build > fails for powerpc. The startcompiler gives a segfault. The reason is probably that the machine you are building on is a G5. For some reason, the Linux kernel people do not turn on a compatibility bit in the G5 which guarantees the same behaviour for the dcbz instruction as on other PPC's (it's meaning is "fill a cache line with zeroes", but cache lines on G5's are 128 bytes as opposed to 32 bytes on other ppc's and many programs, including the FPC rtl, count on that -- which is the reason why this compatibility bit exists and why the G5 also has a dcbzl instruction which zeroes out a full 128 bytes in all cases). Anyway, the result is that too much memory is zeroed out by some RTL routines. You can solve it by disabling all routines rtl/powerpc/ *.inc which include the dcbz instruction and then rebuilding the compiler on a non-G5 machine.

Ok, it seems like that they don't compile on use a mainframe with a 'couple of POWER5 (gr), at 1655.992000MHz'

If I understood correctly they don't support Altivec (VMX?) and are there some other issues.

Is it possible at all to make a power-port? Maybe the power also has the cache-issue, and is that the main problem?

If someone is willing to look at it, but doesn't have a POWER5 machine, he can try to get an account on the Linux on POWER-challende machines?

Any thoughts on this?

Met vriendelijke groeten, Joost van der Sluis CNOC Informatiesystemen en Netwerken http://www.cnoc.nl

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Jonas Maebe
to Joost van der Sluis
Joost van der Sluis wrote 5 lines
Ok, it seems like that they don't compile on use a mainframe with a 'couple of POWER5 (gr), at 1655.992000MHz' If I understood correctly they don't support Altivec (VMX?) and are there some other issues.

FPC doesn't use/generate any altivec/vmx code at this time/

Is it possible at all to make a power-port? Maybe the power also has the cache-issue, and is that the main problem?

Power and PowerPC have been sort of merged quite a while ago already and use the same instruction set now (at least from a non-OS developer point-of-view). But it's indeed quite probable that the cache line size on a Power5 is larger than 32 bytes (the G5 was derived from the Power4).

Jonas

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Jonas Maebe
to Jonas Maebe
Jonas Maebe wrote 5 lines
wer and PowerPC have been sort of merged quite a while ago already and use the same instruction set now (at least from a non-OS developer point-of-view). But it's indeed quite probable that the cache line size on a Power5 is larger than 32 bytes (the G5 was derived from the Power4).

Power5 has mixed 128 (L2) 256 (L3) byte cache lines (slide 18): http://www.cs.utexas.edu/users/cart/arch/fall03/KallaSlides.pdf

Not sure how this works with dcbz, but most definitely not in a way it's used in the RTL.

Jonas

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Joost van der Sluis
to Jonas Maebe
Jonas Maebe wrote 13 lines
On 16 aug 2005, at 17:54, Jonas Maebe wrote: > wer and PowerPC have been sort of merged quite a while ago already > and use the same instruction set now (at least from a non-OS > developer point-of-view). But it's indeed quite probable that the > cache line size on a Power5 is larger than 32 bytes (the G5 was > derived from the Power4). Power5 has mixed 128 (L2) 256 (L3) byte cache lines (slide 18): http://www.cs.utexas.edu/users/cart/arch/fall03/KallaSlides.pdf Not sure how this works with dcbz, but most definitely not in a way it's used in the RTL.

Attached patch fixes the segfault. It's very ugly, so don't commit it! I did use it on Fedora though. Tom tested it on POWER5, which worked.

I don't know how this problem could be solved for good. Maybe someone can rewrite the Move and Fillchar procedures? Those were the only one affected...

Btw: maybe something to put on the website? That fpc now also works on POWER5? (After it's fixed, offcourse)

Joost.

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