I submitted a pull request about a month ago with some bug fixes for the RISC-V 32 embedded target as well as an interrupt vector size adjustment feature at link time and subarch folders to allow different RV32 extension RTLs to co-exist. I had actually fixed the RV32EC register allocator once before about 2 years ago in the main branch, but register allocator code has been completely reworked and the allocator bug is back, allowing registers above x15. There was also another bug for all RISC-V targets where RS_X25 (s9) was missing and RS_X26 duplicated. I have several other bug fixes involving improperly saved registers in the prologue/epilogue code of normal functions, as well as saved volatile regs in interrupt functions, but they are waiting on this PR going through. Is there anything else I need to do to move the PR forward? BTW, I’m not subscribed to the dev list, so CC me for any responses please.

Thanks,
-Matt

Mathew J. Bradford
Principal Engineer
Pinnacle Simulation Systems
801-808-5835