Okay, so I have to specify "-MObjfpc -Sh" to get it to compile due to what the code uses, and the bug still requires the use of -O2 to appear. However... "fpc -MObjfpc -Sh -O2 -Ooregvar -alr -sr breakp.pp" produces a bad binary.
I removed the register comments so it's clearer:
...
# [11] pChar(result)[i] := BarSym[(progress >= (0.75 + i) / divs) or (i = int32(divs) - 1) and (progress >= 1)];
cvtsi2ssl %ireg16d,%mreg34ms
movaps %mreg34ms,%mreg35ms
addss _$BREAKP$_Ld1(%rip),%mreg35ms
movl %ireg18d,%ireg28d
andl $4294967295,%ireg28d
cvtsi2ssq %ireg28q,%mreg37ms
movaps %mreg35ms,%mreg38ms
divss %mreg37ms,%mreg38ms
comiss %mreg32ms,%mreg38ms
jp .Lj12
jbe .Lj10 <---- Register %ireg27q not initialised if this instruction branches to .Lj10
.Lj12:
jmp .Lj11
.Lj11:
movl %ireg18d,%ireg29d
movslq %ireg29d,%ireg30q
subq $1,%ireg30q
movslq %ireg16d,%ireg31q
movq %ireg31q,%ireg27q <---- Problem register: %ireg27q cmpq %ireg27q,%ireg30q
je .Lj14
jmp .Lj15
.Lj14:
comiss _$BREAKP$_Ld2(%rip),%mreg32ms
jp .Lj17
jae .Lj16
.Lj17:
jmp .Lj15
.Lj16:
jmp .Lj10
.Lj15:
jmp .Lj13
.Lj10:
movq $1,%ireg32q
jmp .Lj18
.Lj13:
movq $0,%ireg32q
.Lj18:
movq (%ireg17q),%ireg33q
cmpq $0,%ireg33q
jne .Lj19
leaq FPC_EMPTYCHAR(%rip),%ireg33q
.Lj19:
leaq
TC_$P$BREAKP$_$BAR$SINGLE$LONGWORD$$ANSISTRING_$$_BARSYM(%rip),%ireg34q movb (%ireg34q,%ireg32q,1),%ireg35l
movb %ireg35l,(%ireg33q,%ireg27q,1) <---- Problem register: %ireg27q cmpl %ireg25d,%ireg16d
jge .Lj9
jmp .Lj7
.Lj9:
.Lj6:
...
The problem register is %ireg27q - it's not being initialised if "jbe .Lj10" branches. By your explanation, it seems that the code generator is buggy on one of the nodes. Thanks for the tips in isolating where it could be. To help out, I've attached the node dump file for the test program.
Gareth aka. Kit
Yuriy Sydorov wrote 31 lines
Hi,
On 26.11.2020 17:34, J. Gareth Moreton via fpc-devel wrote:
> Hi everyone,
>
> So a couple of people have reported that -O2 sometimes produces bad
> code under x86_64. So far it seems isolated to that CPU.
>
>
https://bugs.freepascal.org/view.php?id=38129
>
> After my own investigations with the attached code, the problem still
> occurs even if the peephole optimizer is disabled, and the
> uninitialised register is being allocated within conditional code
> that is not always executed, rather than before or after it.
>
> Anyone with any tips on where to dig next (register allocator, node
> converter etc.) would be most appreciated!
First compile with the "-Ooregvar -alr -sr" switches. You will get the
assembler output with imaginary registers and notes about register
allocations and de-allocations. Inspect if all is correct at this
stage. If not then the a code generator of some node is buggy.
Then compile with "-Ooregvar -alr". If the issue is present only at
this stage, then the bug is in the register allocator.
Yuriy.
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