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Mailing lists / fpc-devel / 2020-02

generate assembler with no clear purpose MOV

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Marģers .
 hi
example code:
function roo(lk:longint):byte;
var k : longint;
    bit : longint;
    num : byte;
begin
     num:=0;
     for k:=0 to 25 do
     begin
          bit:= longint(1) shl k;
          if (lk and bit)  0 then
          begin
               lk:=lk xor bit;
               inc(num);
          end;
     end;
     roo:=num;
end;
begin
end.

asm code
# [109] bit:= longint(1) shl k;
    movslq    %ecx,%rdx
    # Register r8d allocated
    movl    $1,%r8d
    # Register edx,edx allocated
    shlx    %edx,%r8d,%edx
    # Register r8d released
    # Register edx allocated
    movl    %edx,%esi
# Peephole Optimization: %esi = %edx; changed to minimise pipeline stall (MovXXX2MovXXX) # Peephole Optimization: Mov2Nop 4 done

what purpose serve: movslq    %ecx,%rdx   ?

movl    %edx,%esi seems unnecessary,
when just enough would be
movl    $1,%esi
shlx    %ecx,%esi,%esi

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Marģers .
to Marģers .

 p.s. tested execution speed and there is no measurable difference.

Show quoted text 12 lines
asm code # [109] bit:= longint(1) shl k;     movslq    %ecx,%rdx     # Register r8d allocated     movl    $1,%r8d     # Register edx,edx allocated     shlx    %edx,%r8d,%edx     # Register r8d released     # Register edx allocated     movl    %edx,%esi # Peephole Optimization: %esi = %edx; changed to minimise pipeline stall (MovXXX2MovXXX) # Peephole Optimization: Mov2Nop 4 done
Show quoted text 9 lines
what purpose serve: movslq    %ecx,%rdx   ? movl    %edx,%esi seems unnecessary, when just enough would be movl    $1,%esi shlx    %ecx,%esi,%esi _______________________________________________ fpc-devel maillist -

https://lists.freepascal.org/cgi-bin/mailman/listinfo/fpc-devel

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J. Gareth Moreton
to Marģers .

To hazard a guess, it's sign-extending to the CPU word size as an intermediate step.  It's not something the peephole optimizer can easily eliminate.  Do the register allocations give any clues before that instruction?

Gareth aka. Kit

Marģers . wrote 29 lines
 p.s. tested execution speed and there is no measurable difference. > asm code > # [109] bit:= longint(1) shl k; >     movslq    %ecx,%rdx >     # Register r8d allocated >     movl    $1,%r8d >     # Register edx,edx allocated >     shlx    %edx,%r8d,%edx >     # Register r8d released >     # Register edx allocated >     movl    %edx,%esi > # Peephole Optimization: %esi = %edx; changed to minimise pipeline stall (MovXXX2MovXXX) > # Peephole Optimization: Mov2Nop 4 done > what purpose serve: movslq    %ecx,%rdx   ? > movl    %edx,%esi seems unnecessary, > when just enough would be > movl    $1,%esi > shlx    %ecx,%esi,%esi > _______________________________________________ > fpc-devel maillist - https://lists.freepascal.org/cgi-bin/mailman/listinfo/fpc-devel _______________________________________________ fpc-devel maillist - https://lists.freepascal.org/cgi-bin/mailman/listinfo/fpc-devel

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Marģers .
to J. Gareth Moreton

 

----- Reply to message -----
Subject: Re: [fpc-devel] generate assembler with no clear purpose MOV Date: otrd., 4 febr. 2020, 22:24
From: J. Gareth Moreton
To:

To hazard a guess, it's sign-extending to the CPU word size as an intermediate step.  It's not something the peephole optimizer can easily eliminate.  Do the register allocations give any clues before that instruction?

# Var k located in register ecx
# Var bit located in register esi

seems to be sign-extend, but if change variable "k" and "bit" to dword then there is simple movl %ecx,%edx. Instruction SHLX (as well SHRX) is treated as variables always are memory variables and there for first read value in temp register and after write back. As well SHL and SHR are logical operators so no need for sign extension. While those MOV instructions do not hurt much, there is benefit of resolving this issue - 2 or 1 free registers available for other purposes.

Show quoted text 22 lines
On 04/02/2020 18:50, Marģers . via fpc-devel wrote: >  p.s. tested execution speed and there is no measurable difference. > > >> asm code >> # [109] bit:= longint(1) shl k; >>     movslq    %ecx,%rdx >>     # Register r8d allocated >>     movl    $1,%r8d >>     # Register edx,edx allocated >>     shlx    %edx,%r8d,%edx >>     # Register r8d released >>     # Register edx allocated >>     movl    %edx,%esi >> # Peephole Optimization: %esi = %edx; changed to minimise pipeline stall (MovXXX2MovXXX) >> # Peephole Optimization: Mov2Nop 4 done > >> what purpose serve: movslq    %ecx,%rdx   ? >> movl    %edx,%esi seems unnecessary, >> when just enough would be >> movl    $1,%esi >> shlx    %ecx,%esi,%esi

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J. Gareth Moreton
to Marģers .

Are you able to dump the nodes as well with -an? (You'll need to define -dEXTDEBUG though) That might give some clues behind the presence of that movslq instruction.

Gareth aka. Kit

Marģers . wrote 45 lines
----- Reply to message ----- Subject: Re: [fpc-devel] generate assembler with no clear purpose MOV Date: otrd., 4 febr. 2020, 22:24 From: J. Gareth Moreton To: > To hazard a guess, it's sign-extending to the CPU word size as an > intermediate step.  It's not something the peephole optimizer can easily > eliminate.  Do the register allocations give any clues before that > instruction? # Var k located in register ecx # Var bit located in register esi seems to be sign-extend, but if change variable "k" and "bit" to dword then there is simple movl %ecx,%edx. Instruction SHLX (as well SHRX) is treated as variables always are memory variables and there for first read value in temp register and after write back. As well SHL and SHR are logical operators so no need for sign extension. While those MOV instructions do not hurt much, there is benefit of resolving this issue - 2 or 1 free registers available for other purposes. > On 04/02/2020 18:50, Marģers . via fpc-devel wrote: >>  p.s. tested execution speed and there is no measurable difference. >> >> >>> asm code >>> # [109] bit:= longint(1) shl k; >>>     movslq    %ecx,%rdx >>>     # Register r8d allocated >>>     movl    $1,%r8d >>>     # Register edx,edx allocated >>>     shlx    %edx,%r8d,%edx >>>     # Register r8d released >>>     # Register edx allocated >>>     movl    %edx,%esi >>> # Peephole Optimization: %esi = %edx; changed to minimise pipeline stall (MovXXX2MovXXX) >>> # Peephole Optimization: Mov2Nop 4 done >>> what purpose serve: movslq    %ecx,%rdx   ? >>> movl    %edx,%esi seems unnecessary, >>> when just enough would be >>> movl    $1,%esi >>> shlx    %ecx,%esi,%esi _______________________________________________ fpc-devel maillist - https://lists.freepascal.org/cgi-bin/mailman/listinfo/fpc-devel

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Marģers .
to J. Gareth Moreton

 

From: J. Gareth Moreton
To:

Are you able to dump the nodes as well with -an? (You'll need to define -dEXTDEBUG though) That might give some clues behind the presence of that movslq instruction.

building compiler with -dEXTDEBUG does not work for me make singlezipinstall OS_TARGET=linux CPU_TARGET=x86_64 OPT="-dEXTDEBUG -CpCOREAVX2 -OpCOREAVX2 -Fu/home/user/fpc304/lib/fpc/3.0.4/units/x86_64-linux/rtl/"

constexp.pas(125,13) Warning: Location (LOC_CSSETREG) not equal to expectloc (LOC_REG): typeconvn
constexp.pas(594) Fatal: There were 1 errors compiling module, stopping

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J. Gareth Moreton
to Marģers .

Hmmm, well that's inconvenient!  Means we can't easily test things with that feature.

Gareth aka. Kit

Marģers . wrote 17 lines
From: J. Gareth Moreton To: > Are you able to dump the nodes as well with -an? (You'll need to define > -dEXTDEBUG though) That might give some clues behind the presence of > that movslq instruction. building compiler with -dEXTDEBUG does not work for me make singlezipinstall OS_TARGET=linux CPU_TARGET=x86_64 OPT="-dEXTDEBUG -CpCOREAVX2 -OpCOREAVX2 -Fu/home/user/fpc304/lib/fpc/3.0.4/units/x86_64-linux/rtl/" constexp.pas(125,13) Warning: Location (LOC_CSSETREG) not equal to expectloc (LOC_REG): typeconvn constexp.pas(594) Fatal: There were 1 errors compiling module, stopping _______________________________________________ fpc-devel maillist - https://lists.freepascal.org/cgi-bin/mailman/listinfo/fpc-devel

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Pierre Muller
to Marģers .:   From: J. Gareth Moreton To: building compiler with -dEXTDEBUG does not work for me…

Le 05/02/2020 à 07:17, Marģers . via fpc-devel a écrit :

Show quoted text 13 lines
  From: J. Gareth Moreton To: > Are you able to dump the nodes as well with -an? (You'll need to define > -dEXTDEBUG though) That might give some clues behind the presence of > that movslq instruction. building compiler with -dEXTDEBUG does not work for me make singlezipinstall OS_TARGET=linux CPU_TARGET=x86_64 OPT="-dEXTDEBUG -CpCOREAVX2 -OpCOREAVX2 -Fu/home/user/fpc304/lib/fpc/3.0.4/units/x86_64-linux/rtl/" constexp.pas(125,13) Warning: Location (LOC_CSSETREG) not equal to expectloc (LOC_REG): typeconvn constexp.pas(594) Fatal: There were 1 errors compiling module, stopping

Some extra warnings are generated when -dEXTDEBUG is iused which lead to errors because -Sew option is used by default.

You will need to also add ALLOW_WARNINGS=1 to the make call.

Pierre

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Marģers .
to Pierre Muller
Show quoted text 8 lines
> From: J. Gareth Moreton > To: >> Are you able to dump the nodes as well with -an? (You'll need to define >> -dEXTDEBUG though) That might give some clues behind the presence of >> that movslq instruction. > You will need to also add ALLOW_WARNINGS=1 to the make call.

Ok, ALLOW_WARNINGS=1 did the job.

in attachment testsh.pas and testsh.s

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