Hello all,

Is there any good generic (portable) function to ensure memory cache flush for a thread on a multicore system?

What I'm trying to do is essentially fetch some debugging counters from multiple threads. They might happen to run on separate cores, thus having something pending in local cache sometimes. I would like to avoid EnterCriticalSection/ LeaveCriticalSection as such blocking would be a huge overkill, however it is still desireable to fetch reasonably current values. I'd like to avoid doing manual assembly as well (for portability reasons etc.).

Thanks a lot!

Nikolai

Have you found this to be a problem in real environments? I can't imagine any of the mainstream processor architectures of FPC where you wouldn't expect normal coherent bus operation when just reading cached memory from other processors. If all you need is just reasonably recent values that is..

Hi,

I have an issue with loading JNI library for Raspberry :(

I do compile with -Cg -WX and stack checking on (and also without).

But even this method is not called :(

function JNI_OnLoad(vm: PJavaVM; reserved: pointer): jint; {$ifdef
linux}cdecl{$else}stdcall{$endif};
begin
   writeln('lll');
   exit(0);
end;

Any suggestions?

Thanks,
Gennady

Java HotSpot(TM) Client VM warning: You have loaded library /media/pi/Transcend/cypress-release/pas2jni_policing64/policing64/policing.so which might have disabled stack guard. The VM will try to fix the stack guard now.

It's highly recommended that you fix the library with 'execstack -c <libfile>', or link it with '-z noexecstack'.

[FORMS.PP] ExceptionOccurred

Sender=EStackOverflow

Exception=Stack overflow

Stack trace:

$62E6CF48 fpc_stackcheck, line 832 of
/home/pi/development/fpc/rtl/inc/system.inc

TApplication.HandleException Stack overflow

Stack trace:

$62E6CF48 fpc_stackcheck, line 832 of
/home/pi/development/fpc/rtl/inc/system.inc

Exception at 62E6CF48: EStackOverflow:

Stack overflow.

2016-10-31 19:33 GMT+01:00 Nikolai Zhubr :

Maybe: http://www.freepascal.org/docs-html/rtl/system/readwritebarrier.html

Vincent

31.10.2016 22:44, Jeppe Johansen:

No.

I can't imagine any of the mainstream processor architectures of FPC where you wouldn't expect normal coherent bus operation when just reading cached memory from other processors. If all you need is just reasonably recent values that is..

Ok. Probably you are right.
Thanks!

Nikolai

Surely that shouldn't happen on a properly-implemented cache-coherent system?

Gennady Agranov wrote

Hi, I have an issue with loading JNI library for Raspberry :(

what does this have to do with the "A generic function for (multicore) cache flush?" topic you attached it to by replying to that topic? you should use the [write] or [post] button and then type in the name of the mailing list or news group... then the subject and the post instead of trying to take shortcuts and hijacking a topic...

I thought that "reply" and changing the subject to a new one will do the trick...

Is "topic" stored somewhere in the mail headers?

Sorry,
Gennady

Why do you use LCL in your JNI library?
Try a simple library without LCL and check if it loads. Also do not add any extra compiler switches.
In FPC 3.0 -Cg is broken for ARM.

Yury.

Gennady Agranov wrote

I thought that "reply" and changing the subject to a new one will do the trick... Is "topic" stored somewhere in the mail headers?

There is an "In-Reply-To" header, which states to which message your message is a reply. All related replies are grouped into the same topic by most mail clients.

Jonas

31.10.2016 23:07, Vincent Snijders:

Oh yes! That's the thing!
Thanks a lot!

Nikolai

Vincent