I am currently writing/porting startup code for the pic32 chips, the inline assembler of fpc seems to lack support for some opcodes, any idea how I can workarround this?

With grep I found for example mtc1 in opcode.inc, but mtc0 is missing, this opcode is important for the initialization of the pic32 chips.

Is it easy to implement those missing op-codes in the internal assembler, if yes, could some fpc-crack give me a hint on what to change where?

Those are the missing opcodes:

beqz
ehb
ext
ins
mfc0
mtc0
sdbbp
wrpgpr

Thank you in advance,

Michael

28.05.2013 22:50, Michael Ring пишет:

Since assembler reader for MIPS is at a very early stage, adding opcodes isn't difficult:

1) Add the opcode enum to mips/opcode.inc and its string representation to mips/strinst.inc.
2) For 'ext' and 'ins' you'll need to add the appropriate overloaded constructor to taicpu class in mips/aasmcpu.pas (they are going to be the first opcodes with 4 operands)
3) Modify taicpu.spilling_get_operation_type method (in mips/aasmcpu.pas) to reflect which operands are read/written by newly added opcodes.

A more difficult task will be to restrict opcodes to CPU type and operands to opcodes.

Note that 'beqz reg,label' is just a shorter representation of 'beq reg,$zero,label', not a separate opcode (unlike bgtz/bltz/blez/bgez which are really missing).

Regards,
Sergei

Thank you Sergei, I will have a look at that code.

I have just finished inserting ugly .long 0xxxxxx statements in my code to hardcode the missing pieces, I am really glad you answered ;-) ;-)

I also found some statements that get translated wrong:

and $a0,$a0,0

and $a1,$a1,0

li $t2,0

the statements are missing the last param in the generated assembler file:

pic32mx1xxfxxxb.s:87: Error: absolute expression required `li $t2,' pic32mx1xxfxxxb.s:102: Error: absolute expression required `and $a0,$a0,'

I guess this needs to be fixed in mips/aasmcpu.pas

Michael

28.05.2013 23:40, Michael Ring пишет:

That's strange, at least 'li' is present in RTL MIPS-specific assembler routines and it seems to be handled correctly.

Regards,
Sergei

I did the changes, parts of the opcodes now work fine, I think I have found the problem with the li + and + mfc0 op-codes, if last parameter is 0 then the asm statement is generated wrong:

This works:
and $a0,$a0,1

this does not work:
and $a0,$a0,0

result is:

pic32mx1xxfxxxb.s:107: Error: absolute expression required `and $a0,$a0,'

I am now having troubles with the syntax for mfc0 and mtc0:

mfc0 $t0,$12, 1 //_CP0_STATUS

gets translated to:

mfc0 $t0,$t4,1

which the assembler does not like, it needs $12 and not $t4:

pic32mx1xxfxxxb.s:37: Error: Illegal operands `mfc0 $t0,$t4,1'

Any ideas what to do here?

Michael

Index: opcode.inc
=================================================================== --- opcode.inc (revision 24626)
+++ opcode.inc (working copy)
@@ -206,4 +206,11 @@
A_SHL64SUB,
A_SHR64SUB,
A_XOR64SUB,
+A_EHB,
+A_EXT,
+A_INS,
+A_MFC0,
+A_MTC0,
+A_SDBBP,
+A_WRPGPR,
A_END_DEF
Index: aasmcpu.pas
=================================================================== --- aasmcpu.pas (revision 24626)
+++ aasmcpu.pas (working copy)
@@ -57,6 +57,7 @@

      constructor op_reg_reg_ref(op: tasmop; _op1, _op2: tregister;

const _op3: treference);

      constructor op_reg_reg_const(op: tasmop; _op1, _op2: tregister;

_op3: aint);

      constructor op_reg_const_reg(op: tasmop; _op1: tregister; _op2:

aint; _op3: tregister);
+ constructor op_reg_reg_const_const(op: tasmop; _op1: tregister; _op2: tregister; _op3: aint; _op4: aint);

      { this is for Jmp instructions }
      constructor op_sym(op: tasmop; _op1: tasmsymbol);
@@ -196,6 +198,15 @@
    loadreg(2, _op3);
  end;
+constructor taicpu.op_reg_reg_const_const(op: tasmop; _op1: tregister;
_op2: tregister; _op3: aint; _op4: aint);
+begin
+  inherited create(op);
+  ops := 4;
+  loadreg(0, _op1);
+  loadreg(1, _op2);
+  loadconst(2, _op3);
+  loadconst(3, _op4);
+end;

  constructor taicpu.op_sym(op: tasmop; _op1: tasmsymbol);
  begin

@@ -397,7 +408,10 @@
A_SGTU,
A_SLE,
A_SLEU,
- A_SNE];
+ A_SNE,
+ A_EXT,
+ A_INS,
+ A_MFC0];

        begin
          result := operand_read;

Index: strinst.inc
=================================================================== --- strinst.inc (revision 24626)
+++ strinst.inc (working copy)
@@ -206,4 +206,11 @@
'shl64sub',
'shr64sub',
'xor64sub',
+'ehb',
+'ext',
+'ins',
+'mfc0',
+'mtc0',
+'sdbbp',
+'wrpgpr',
'end_def'

29.05.2013 1:26, Michael Ring пишет:

So it is the value of operand that matters. I'll try to look at it, probably a bug in the parsing part, because the output part doesn't have anything suspicious.

This one is more complicated, we need at least to prevent register name translation (since $12 is a coprocessor register, not a general-purpose one), at most handle such registers as a different register type.

Regards,
Sergei

29.05.2013 2:08, Sergei Gorelkin пишет:

Fixed in r24630. The parsing part is buggy as hell (it interprets numbers as references rather than as constants), but the output part wasn't correct either at outputting such references.

Regards,
Sergei

This is looking good now on first view, all statements seem to pass through now.

The only thing not working is the register error in mfc0 (and friends) command.

Now I will wade through some more code to find out why my nice param -CpMIPS32R2 is ignored by assembler, it still defaults to MIPS2:

Target OS: Embedded
Compiling pic32mx1xxfxxxb.pp
Assembling pic32mx1xxfxxxb
pic32mx1xxfxxxb.s: Assembler messages:
pic32mx1xxfxxxb.s:37: Error: Illegal operands `mfc0 $t0,$t4,1' pic32mx1xxfxxxb.s:38: Error: Opcode not supported on this processor: mips2 (mips2) `ext $t0,$t0,19,1'
pic32mx1xxfxxxb.s:49: Error: Opcode not supported on this processor: mips2 (mips2) `ext $t2,$t1,26,4'
pic32mx1xxfxxxb.s:51: Error: Opcode not supported on this processor: mips2 (mips2) `ins $t1,$t2,6,4'

Thank you for your help!

Michael

29.05.2013 21:44, Michael Ring пишет:

I hopefully fixed this issue in r24643, and the register naming issue in r24799. Should you encounter more issues, do not hesitate to report them.

Regards,
Sergei

As an aside, is Fuxin Zhang (Lemote) still active in here? I've not seen anything from him here since last year but he posted to debian-mips a couple of days ago.

Mark Morgan Lloyd wrote

As an aside, is Fuxin Zhang (Lemote) still active in here? I've not seen anything from him here since last year but he posted to debian- mips a couple of days ago.

No, he unsubscribed on 23 April.

Jonas

Thanks for that, I was worried that something untowards had happened at Lemote. I wonder whether they managed to deploy machines with FPC on them?

Thank you, the startup code is compiling now, I will send you a patch with the missing opcodes to have full support of mips32r2 soon.

Michael

I have now browsed through the current mips documentation and have created a file that includes all opcodes, the version they are first in (starting with mips32) and a small comment what the mnemonic does. This file is attached to this mail.

Out of this file it is easy to create both compiler/mips/strinst.inc and compiler/mips/opcode.inc.

Now I am looking for additional lines that I will need to add to this file, to find out what is necessary I have created a list of mnemonics that exist only in the original opcode.inc file (see later)

there are a number of entries in the form xxx64xxx and xxx32, xxxg and dxxx, all those do not seem to be valid for mips32 & up, where do those come from and which of those do I need to add?

There's one very strange entry in opcode.inc: 'b '

there is also 'b', is it necessary to have 'b ' ?

Thank you,

Michael

'add64sub',
'b ',
'dadd',
'daddi',
'daddiu',
'daddu',
'ddiv',
'ddivg',
'ddivu',
'ddivug',
'div64sub',
'divg',
'divug',
'dli',
'dmfc1',
'dmodg',
'dmodug',
'dmtc1',
'dmul',
'dmulo',
'dmulou',
'dmult',
'dmultg',
'dmultu',
'dmultug',
'dneg',
'dnegu',
'drem',
'dremu',
'dsll',
'dsll32',
'dsllv',
'dsra',
'dsra32',
'dsrav',
'dsrl',
'dsrl32',
'dsrlv',
'dsub',
'dsubu',
'end_def'
'la',
'ld',
'ldl',
'ldr',
'li',
'lld',
'lwu',
'modg',
'modug',
'move',
'mul64sub',
'mulo',
'mulou',
'multg',
'multug',
'neg',
'neg64sub',
'negu',
'not',
'not64sub',
'or64sub',
'rem',
'remu',
'sar64sub',
'scd',
'sd',
'sdl',
'sdr',
'seq',
'sge',
'sgeu',
'sgt',
'sgtu',
'shl64sub',
'shr64sub',
'sle',
'sleu',
'sne',
'sub64sub',
'xor64sub',

16.06.2013 22:17, Michael Ring пишет:

The problem here is that MIPS32 is not the first, but fifth version of MIPS instruction sets, preceded by MIPS I, MIPS II, MIPS III and MIPS IV. Currently there is no separation between instructions sets in compiler sources, but they need to appear one day. MIPS32 documentation is not correct in this respect, as it says e.g. that ADD is first supported by MIPS32, while it is actually MIPS I instruction.

The most accurate source is probably the GNU Opcode library, which is part of binutils.

xxx64xxx and xxxg are likely subject for removal, I've no idea where they came from. dxxx and xxx32 are MIPS III instructions, as well as sdr,sdl,lwu and alike. A lot of other stuff (la, li, neg, mulo, seq, etc.) are macros that are expanded into several instructions.

There's one very strange entry in opcode.inc: 'b ' there is also 'b', is it necessary to have 'b ' ?

The codegenerator and optimizer expect conditional and unconditional branches to have distinct opcodes, this strange construction provides that.

Regards,
Sergei

I did have a in binutils, this looks easy to parse, I will give this a try, thank you for the hint!

I will come back to you with a 2nd version, looks like a nice task to complete while sitting in the train....

Michael