Is there a reason why MM_MaskInvalidOp is not set in mxcsr in rtl/x86_64/x86_64.inc?

I have a 3rd party application that depends on InvalidOp to be masked out. I want to extend this application with a FPC library. But the initialization code of the library (SysInitFPU) unmasks the InvalidOp exception.

I now call "SetSSECSR(GetSSECSR or $0080);" in the initialization section of my main unit to mask out the InvalidOp exception again. But I wonder if this could break something (in rtl or internal FPC functions). I fear it is unmasked on purpose in SysInitFPU because according to the Intel documentation (Intel Software Developers Manual 2A) "The default MXCSR value at reset is 1F80H."

Markus Beth wrote

Is there a reason why MM_MaskInvalidOp is not set in mxcsr in rtl/x86_64/x86_64.inc?

Because on all FPC platforms, the default behaviour is that an invalid floating point operation causes an exception.

I have a 3rd party application that depends on InvalidOp to be masked out. I want to extend this application with a FPC library. But the initialization code of the library (SysInitFPU) unmasks the InvalidOp exception.

That's this problem: http://bugs.freepascal.org/view.php?id=16263

I now call "SetSSECSR(GetSSECSR or $0080);" in the initialization section of my main unit

You should use math.SetExceptionMask instead, the above can lead to inconsistent situations.

to mask out the InvalidOp exception again. But I wonder if this could break something (in rtl or internal FPC functions).

No, unless you have code that depends on exceptions being generated for invalid floating point operations.

Jonas