Hello,

The attached patch implements i386-specific codegeneration for 32 -> 64 bits multiplications, approximately as described in "FPC HowToDo" wiki page. I also copied the generic part from tcgaddnode into ti386addnode.second_mul, so that all multiplications are handled in a single procedure. Although there was no absolute need to do that, it makes the code easier to understand.

Regards,
Sergei

Sergei Gorelkin wrote

The attached patch implements i386-specific codegeneration for 32 -> 64 bits multiplications, approximately as described in "FPC HowToDo" wiki page.

Thanks!

I also copied the generic part from tcgaddnode into ti386addnode.second_mul, so that all multiplications are handled in a single procedure. Although there was no absolute need to do that, it makes the code easier to understand.

Could you rewrite it so it does not do that? I have already fixed several times in the past code generator bugs which were fixed for one architecture but not for another (or not in the generic code) exactly due to this sort of duplication.

Thanks,

Jonas

Done, attached is a modified patch witout duplication.

Regards,
Sergei

Thanks, comment with one small change: you cannot first release both EDX and EAX, then allocate 2 new registers and move EDX and EAX into them. The reason is that in this case the first allocated register may be mapped to EAX by the register allocator, so you can get this in the end:

movl %edx, %eax
movl %eax, %ecx

or even

movl %edx, %eax
movl %eax, %edx

Jonas