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fpc-devel · 2025-09

  1. ASM One register allocated twice at once ? 3.3.1 peephole / # Register r10, r15, r15 allocated

    3.3.1 d3ac07ad274b6c6b09ff9b08a9d7007aaf780aa6 I am currently tracking an issue (either my code, or the peephole opt / or some opt+peephole). While going through the asm…

    Martin Frb, J. Gareth Moreton
    2
  2. Do type-helpers block "regvar" opt?

    Tested with 3.3.1  d3ac07ad27 -O4 Win 64 bit In the code below, compiled with -alr    .section .text.n_p$project1_$$_foo,"ax"    ....    # Var a located in…

    Martin Frb, Sven Barth
    3
  3. RISC-V separating Zicsr and Zifencei from base ISA

    A while ago the GNU RISC-V toolchain [1] implemented separation of the Zicsr and Zifencei options from the base integer ISA according to the ISA spec 20191213. …

    Christo Crause
    0
  4. Support for PowerPC64 on FreeBSD

    I’m attempting to build fpc on FreeBSD/PowerPC64. I’ve added what I think are the necessary changes to add PowerPC64 to BSD/FreeBSD. However, when I cross compile…

    Curtis Hamilton
    0
  5. if-then-else expression

    Hello together! Time for the next flame. I've attached a patch which implements an "if Condition then ThenExpr else ElseExpr"-expression for those that want to play…

    Sven Barth, Benito van der Zander, Hairy Pixels
    26